The present invention relates to bidimensional filters of the finite impulse response (FIR) type such as used especially for encoding TV pictures, for example for achieving a so-called "subband" encoding. In this application, the invention will be described in relation to the processing of a TV picture in which a memory contains the successive pixels of a picture. However, it is clear that the invention applies generally to the filtering of data arranged according to a bidimensional matrix.
Given a picture constituted by pixels Pij, as represented in FIG. 1, where i is a line index included between 1 and M, and j is a column index included between 1 and N, bidimensional FIR filtering comprises performing operations of linear combination on sequences of one-line pixels and on sequences of one-column pixels. It is said that the filtering is of rank 2p+1 if the considered sequence is a sequence associating 2p+1 successive pixels.
Thus, vertical filtering is defined by the following relation (1): ##EQU1## where Ck designates a coefficient, and horizontal filtering is defined by the following relation (2): ##EQU2## where Dk designates a coefficient.
These operations being linear, it will be noticed that the order of the horizontal and vertical filtering operations is of no consequence.
FIG. 2 is a diagram of a conventional FIR filter, used as a basis for the construction of a horizontal or vertical filter. This filter includes a series of identical modules M.sub.1 to M.sub.2p+1. In the figure, module M.sub.2 only is identified by a frame drawn in dotted lines. This module comprises a data input terminal e2 of a multiplier 1-2 where the input datum is multiplied by a coefficient C2. The figure shows the datum arriving on a single line. In fact, this datum is generally a binary word of several bits and input e2 corresponds to a bus comprising as many lines as bits included in the word. The output of multiplier 1-2 is sent to the first input of an adder 2-2, the second input of which receives the output of the preceding module. The adder output is connected to the input of a sampling register 3-2 which corresponds to a clock edge. The output of sampling register 3-2 is connected to the second input of the adder of the next module. All these registers are controlled by a clock CK which enables, at the introduction rate of the data, reading the datum present at the output of the preceding adder and sending the previously stored datum to the next adder.
It will be clear that such a filter, all the inputs of which are interconnected, enables performance of the operation indicated by formula (1). Indeed, considering the case where p=2 (5 modules), and assuming that data p1 . . . pn are successively introduced, output S provides at the sixth clock time: EQU Q13=C1 P11+C2 P12+C3 P13+C4 P14+C5 P15,
at the seventh clock time: EQU Q14=C1 P12+C2 P13+C3 P14+C4 P15+C5 P16,
and so forth.
Various correction techniques are known by those skilled in the art to provide, if necessary, data Q11, Q12 which are available with the elementary circuit described above. Thus, in the conventional case where the data matrix, namely a TV pixel image is scanned by horizontal lines, the row data sequentially arrive and the filter easily lends itself to horizontal filtering.
But, for vertical filtering, pixels P11, P21, P31 . . . PM1 are to be sequentially provided to the filter before processing pixels P12, P22 . . . PM2. This implies, still in the case of conventional horizontal scanning, to provide upstream of the filter delay lines having substantially the duration of a line. For a filter of rank 2p+1, 2p delay lines are to be provided. Such an architecture is for example described in the Article by Rao et al., Proceedings of IEEE International Symposium on Circuits and Systems, New Orleans, La., May 1990, pages 3050-3052. The delay lines are conventionally achieved by memories and, for example, for a filter of rank 17 and pixels defined on 8 bits, 16 memories connected to the filter through 16 buses of 8 bits are to be provided. If the filter and the delay lines are achieved in various chips, this requires, for the filter chip, the provision of an extremely high number of pads, with a resulting very expensive casing (the cost of an integrated circuit casing increasing very quickly with the number of pins of this casing) and a limited efficiency. Consequently, it has been proposed to include the memories serving as delay lines in the filter chip. But then, the chip has a very large silicon surface. In addition, the optimized technologies for manufacturing memories are generally not the same as those used for manufacturing filter cells. As a result, the chip of the assembly is not optimized. Anyhow, this integration of filters and memories on a single chip becomes impossible when the rank of the filter becomes too high, for example 65, or when the data words to be processed contain too many bits, for example 16 or 32.
This problem is all the more crucial as, in some TV circuits, for example those provided for high definition TV, in which it is desired to use a subband encoding technique, several filters are provided in a single TV set.